Adaptive Computing Systems (ACS) built from configurable logic processors offer the performance of supercomputers on many classes of bit/byte oriented problems at a fraction of the cost. There are, however, substantial labor costs associated with programming such ACS machines, which is the key weakness of current systems. Presently, such systems require detailed, low-level design of hardware, runtime systems, and host-interface by a team of hardware designers, systems programmers, and applications programmers. The compiler developed in this project  makes adaptive configurable-logic-based platforms accessible to the wider community of software programmers by supporting a C language synthesis facility.

The goal of this project is to develop efficient compiler technology to map high level parallel-C language descriptions into circuits for Field Programmable Gate Arrays (FPGAs) under the control of a software engineer with application-specific knowledge. Our  objective is to eliminate the need for expertise in the hardware design by automatically synthesizing efficient hardware realizations of C language modules. Instead, we ask the programmer to understand parallel programming in the Communicating Sequential Processes (CSP) model, and further to understand the architecture and communications paths of the FPGA board. Thus the programmer can write a parallel C program mapped to a parallel architecture, and get back customized hardware circuits synthesized to a board containing FPGAs.

Streams-C is available in source form for non-commercial use (see the Download page). Our compiler uses the SUIF 1.3 compiler infrastructure (available from the SUIF Web Page) and runs on Linux PC's. We add two passes to the SUIF compiler flow, one for analysis and scheduling, and one for VHDL generation. The compiler can pipeline inner loops and can unroll loops. It automatically schedules memory access from external memories. The sc2 compiler generates scheduled RTL VHDL. Our release targets the Annapolis Microsystems Firebird FPGA board, and can be easily re-targeted to other FPGA boards.

In addition to the synthesized VHDL, we include a VHDL library and a Firebird-specific runtime library. The supporting runtime environment includes communications and synchronization primitives, the host program, logic array initialization and configuration loading, reading and writing data from logic array to host.

The Streams-C release also includes a simulation package that supports simulation of the parallel processes at a functional level on a Linux PC.